Many data processor architectures now incorporate multiple execution units to simultaneously perform more than one instruction at a time. Such an architecture can greatly increase the throughput of a data processing system with respect to another system that has a single general purpose execution unit or that waits until a first instruction completes before beginning a second subsequent instruction. For instance, a data processor may have an integer execution unit, a floating point execution unit, a data execution unit and an instruction execution unit. Each of these execution units is only able to perform a few instructions. Collectively, however, they can perform a complete set of instructions required by a general purpose data processor. In addition, these four execution units may perform up to four separate instructions at the same time depending upon various factors.
Data processors that incorporate multiple execution units may be further classified by the protocol they follow when "writing back" instruction results to architectural registers. Write back is the procedure a data processor follows when it writes the results of a completed instruction to an architectural register. The data processor may either write back "in-instruction-order" or "out-of-instruction-order." The selection of a write back protocol is a compromise between hardware and software complexity. It is simpler to program an in-instruction-order data processor to handle interrupts and exceptions, for instance, than it is to program an out-of-instruction-order data processor to handle the same events. Conversely, it is simpler to design an out-of-instruction-order data processor than it is to design an in-instruction-order data processor.
An "in-instruction-order" data processor is one that updates architectural registers with the result of an instruction in the order in which the instructions appear in the original instruction stream. An in-instruction-order data processor may use a rename buffer to temporarily store its results prior to write back because the results may not necessarily complete in the original instruction order. Instructions may complete out of order because they began out of order, because different types of instructions take different amounts of time to complete, or both. In operation, the first result is written from the rename buffer to the appropriate architectural register once the first instruction completes. The second result is written from the rename buffer to the second architectural register once the second instruction completes and the first instruction is written back, etc.
An "out-of-instruction-order" data processor is one that updates architectural registers with the result of an instruction in the order in which the instructions complete in the various execution units. Once the execution unit completes the instruction, it writes its result directly to the architectural register without any consideration of instruction order. Therefore, the write back order of an out-of-instruction-order data processor may or may not coincide with the original instruction order.
Known in-instruction-order data processors have their complexity increased or their performance reduced to account for the large number of data dependencies that may exist among a group of instructions. These data dependencies must be accounted for if multiple instructions are to be executed simultaneously. For instance, an execution unit may require data from an architectural register that has yet to be determined by a previous instruction. The same architectural register unit may be modified by two or more previous instructions. In the first case, the execution unit must wait until the previous instruction completes before the data will be valid. In the second case, the execution unit must wait for the second previous instruction to complete before its data is valid. The execution unit, however, must not mistakenly read the value of the architectural register immediately after the first of the two previous instruction completes.